Along with the development of a semiconductor manufacturing process for manufacturing semiconductor integrated circuit devices, a field-effective type transistor (hereinafter, referred to as MOSFET) for use in constituting a circuit formed in the semiconductor chip has been further miniaturized. By the miniaturization of the MOSFET, a gate oxide film to be formed between a gate of the MOSFET and a semiconductor substrate is made further thinner. As the gate oxide film is made further thinner, the withstand voltage against breakdown relative to a voltage applied to the gate is lowered conspicuously. As the voltage applied to the gate, a high voltage generated by static electricity that is generated upon transportation or handling of the semiconductor integrated circuit device is included. For this reason, an electrostatic damage (ESD) test is executed on the semiconductor integrated circuit device so as to improve portions in which the withstand voltage against breakdown is lowered.
As such an electrostatic damage test, a CDM (Charged Device Model) test is carried out. The CDM is one of electrostatic discharge models in the semiconductor integrated circuit device. In the CDM test, the entire semiconductor integrated circuit device is set to an electrified state, and a test-use terminal is selected from a plurality of terminals disposed on the semiconductor integrated circuit device, so that a metal terminal is made in contact with the selected terminal. When made in contact therewith, the metal terminal is supplied with a ground voltage of the circuit. By this contact, the electrified charge is discharged through the selected test-use terminal so that the CDM withstand voltage is evaluated.
In the CDM test, in circuits that receive signals from circuits that are operated by different power-supply voltages, the gate of the MOSFET tends to be damaged. Patent Document 1 has disclosed a technique for preventing the electrostatic damage of the gate caused by the CDM test by using a small number of protective circuits.